Cryptographic Hardware and Embedded Systems - CHES 2004: 6th by Jason Waddle, David Wagner (auth.), Marc Joye, Jean-Jacques

By Jason Waddle, David Wagner (auth.), Marc Joye, Jean-Jacques Quisquater (eds.)

This booklet constitutes the refereed lawsuits of the sixth foreign workshop on Cryptographic and Embedded platforms, CHES 2004, held in Cambridge, MA, united states in August 2004.

The 32 revised complete papers awarded have been rigorously reviewed and chosen from a hundred twenty five submissions. The papers are prepared in topical sections on part channels, modular multiplication, low assets, implementation points, collision assaults, fault assaults, implementation, and authentication and signatures.

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Example text

Guess space assumption: the predicted value of the targeted bit for any wrong sub-key guess does not depend on the value associated to the correct guess. 3. Time space assumption: the power consumption W does not depend on the value of the targeted bit except when it is explicitly handled. But when confronted to the experience, the attack comes up against the following facts. Fact A. For the correct guess, DPA peaks appear also when the targeted bit is not explicitly handled. This is worth being noticed albeit not really embarrassing.

This can be done using a selection function D that we define as follows. Let and be two consecutive values inside a target register. An estimation of the register power consumption at the time of the transition is given by the function An attacker who has to predict the transitions inside the registers of an implementation therefore needs to answer two basic questions: 1. Which register transitions can we predict? 2. Which register transitions leak information? Answering these questions determines which registers will be targeted during the attack.

Such a behavior can be observed on a wide variety of chips even those implementing 16 or 32-bit architectures. Correlation rates ranging from 60% to more than 90% can often be obtained. Figure 2 shows an example of partial correlation on a 32-bit architecture: when only 4 bits are predicted among 32, the correlation loss is in about the ratio which is consistent with the displayed correlations. This sort of results can be observed on various technologies and implementations. Nevertheless the following restrictions have to be mentioned: Sometimes the reference state is systematically 0.

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