Analog Circuit Design - High-Speed Clock And Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

Analog Circuit layout comprises the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and worthy layout principles within the region of analog circuit layout. each one half is gifted through six specialists in that box and cutting-edge info is shared and overviewed. This ebook is quantity 17 during this winning sequence of Analog Circuit layout.

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8, showing the pulse peak response of the channel of Fig. 2 varying the equalizer boost at Nyquist frequency (x-axis), while matching the low frequency channel reverse function. When the input signal is crosstalk, the channel response is completely different. Xtalk Channel TX + VMA VMA*vpku 0dB Fig. 6 Equalizer modeling: 0 dB boost and gain Gain 22 M. Pozzoni et al. C0 Nyquist freq. Monotone C1 Ideally equalized channel C-1 a) b) Monotone C2 C3 C4 Fig. 7 Effect of the 0 dB boost equalizer on pulse peak Fig.

A 10 Gb/s 5-Tap-DFE-4-Tap-FFE transceiver in 90 nm CMOS”, ISSCC Dig. of Tech. Papers, pp. 80–81, Feb. 2006. 4. K. J. Wong, C. K. Yang, “A Serial-Link Transceiver with Transition Equalization”, ISSCC Dig. of Tech. Papers, pp. 82–83, Feb. 2006. 5. Fibre Channel, “Physical Interface-4 (FC-PI-4)”, Int. Committee for Information Technology Standardization (INCITS), Rev. 7, Sept. 2007. 6. R. Kajley, P. Hurst, “A Mixed-Signal Decision-Feedback Equalizer That Uses a Look-Ahead Architecture”, IEEE J.

Two main aspects can be mentioned in duobinary signaling: r r the signal at Nyquist is not recovered; the channel is well equalized (within 3 dB loss) up to Nyquist/2. As shown in Fig. 24, the duobinary detector makes use of two samplers, with the following detecting logic: r r r If threshold A is exceeded, a ‘1’ is detected If threshold B is not exceeded, a ‘0’ is detected If threshold B is exceeded but threshold A is not exceeded, the detected bit is assumed to be reverse of the previous detected bit.

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